Hardroc 3B

RPC and gaseous detector semi-digital read-out chip

hardroc3b

 

HARDROC 3B is a 64-channel front-end ASIC designed to readout negative fast (<1ns) and short (<10ns) current pulses from various detectors (Resistive Plate Chambers, Multi Anode Photo Multipliers, …). HARDROC 3B provides a semi-digital readout with three thresholds tunable between 10 fC up to 10 pC and integrates a 8-depth digital memory per channel to store the 2 encoded outputs of the 3 discriminators upon channel trigger. The three thresholds are set by three integrated 10-bit DACs. The gain of each channel can be tuned individually from 0 to 2 over 8 bits, allowing the compensation of non-uniformity between the 64 detector channels. Each channel is trigger-wise independent and can auto-trigger on signal down to 10 fC. A multiplexed charge measurement allows linear analogue measurement up to 30pC.
The power consumption is 2.5 mW/channel and the chip can be fully power-pulsed allowing a significant power reduction by disabling unused blocks.


TRL Technology Readiness Level  9 - Full system runing ASIC, reliability proven - learn more
Available versions
  • Hardroc 3B : available
  • Hardroc 3A : discontinued
Detector Read-Out  RPC, MA-PMT
Number of Channel 64
Signal Polarity Negative
Sensitivity Trigger on 10 fC with 100% efficiency
Timing Resolution  Time stamping 200ns
Dynamic Range 30 pC
Packaging & Dimension 
  • TQFP 208 28x28mm
Power Consumption

2.5 mW /ch, power supply: 3.3V
power pulsing

Inputs 64 current inputs
Outputs
  • 2 encoded data outputs per channel streamed out in serial
  • 1 multiplexed charge output
  • 3 multiplexed trigger outputs or 3 trigger 0R of the 64 channels
Internal Programmable Features
  • gain adjustment between 0 and 2 over 8 bits for each input preamp
  • trigger threshold adjustment (10bits)
  • 3*64 trigger masks
  • I2C programmable
Evaluation systems
  • Evaluation board : Available

hardroc3B

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Hardroc 3B product manager is Salleh Ahmad

 

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