library  IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;

entity RSwithTimeOut is
port (
	OR_t_delayed	:	IN STD_LOGIC ;
	EN_TimeOut	:	IN	STD_LOGIC;
	reset		: 	IN	STD_LOGIC;
	ck			: 	IN	STD_LOGIC;
	RS_TimeOut	:	out	std_logic;
	SPY1		:	out	std_logic;
	SPY2		:	out	std_logic;
	SPY3		:	out	std_logic
	 );
end RSwithTimeOut;

architecture rtl of RSwithTimeOut is

	SIGNAL reset_RShold	:	Std_Logic;
	SIGNAL TimeOut		:	STD_LOGIC;
	signal rst_TimeOut	:	std_logic;
	signal RS			:	std_logic;
	signal q_sig		:	Std_Logic_Vector(3 downto 0);

COMPONENT count4timeout IS
	PORT
	(
		clock		: IN STD_LOGIC ;
		cnt_en		: IN STD_LOGIC ;
		sclr		: IN STD_LOGIC ;
		cout		: OUT STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
	);
END COMPONENT;

begin

reset_h: process (reset, EN_TimeOut, ck)
begin
if (reset = '1' OR EN_TimeOut ='0') then
	TimeOut		<= '0';
else
	if ck'Event and ck = '0' then
		TimeOut  	<= rst_TimeOut;
	end if;
end if;
end process reset_h;

count4timeout_inst : count4timeout PORT MAP (
		clock	 => ck,
		cnt_en	 => RS,
		sclr	 => reset_RShold,
		cout	 => rst_TimeOut,
		q	 => q_sig
	);

RS <= (RS OR OR_t_delayed) AND NOT(reset_RShold);

reset_RShold <= TimeOut OR reset;

RS_TimeOut <= RS;

SPY1	<= reset_RShold;
SPY2	<= TimeOut;
SPY3	<= RS;

end rtl;
