LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.numeric_std.all;
USE ieee.std_logic_unsigned.all;

ENTITY Firmware_v IS
	PORT (
			n_reset		: IN STD_LOGIC ;
			n_read		: IN STD_LOGIC ;
--			clock_machine	: IN STD_LOGIC ;
			subadd		: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
			user_data	: INOUT STD_LOGIC_VECTOR (7 DOWNTO 0);
			word_100	: INOUT	STD_LOGIC_VECTOR (7 DOWNTO 0)
		);
END Firmware_v;

ARCHITECTURE SYN OF Firmware_v IS
	SIGNAL sel_word		: Std_Logic;

COMPONENT Read_Word
	PORT
	(
	reset		: IN	STD_LOGIC;
	n_read		: IN	STD_LOGIC;	-- horloge pour la sm et l'ADC
	selection	: IN	STD_LOGIC;	-- selection lecture 
	word_x		: IN	STD_LOGIC_VECTOR(7 DOWNTO 0); -- registre à lire
	User_Data	: INOUT	STD_LOGIC_VECTOR(7 DOWNTO 0) -- bus USB
	);
END	COMPONENT;

BEGIN

-- USB Read instantiation        // Machine de lecture du Word 0 (ecriture sur bus USB)
Read_Word0 : Read_Word PORT MAP (
		reset		=> n_reset,
		n_read		=> n_read,
		selection	=> sel_word, 
		word_x		=> word_100,	-- registre à lire
		User_Data	=> user_data -- bus USB
	);

make_sel_word : PROCESS(subadd)
BEGIN
	CASE subadd IS
	WHEN "1100100"	=>	sel_word <= '1';	-- add(word_100) = 0
	WHEN OTHERS	=>	sel_word <= '0';
END CASE;
END PROCESS make_sel_word;

END SYN;
