LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY latch_8 IS
	PORT (
			aclr	: IN STD_LOGIC ;
			n_write	: IN STD_LOGIC ;
			data	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
			sel_word: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
			word0	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
			word1	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
			word2	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
			word3	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
			word4	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
			word5	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
			word6	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
			word7	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
END latch_8;

ARCHITECTURE SYN OF latch_8 IS


component reg_8bits
	PORT
	(
		aclr		: IN STD_LOGIC ;
		clock		: IN STD_LOGIC ;
		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		enable		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
end component;


SIGNAL clock: STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN
-- instantiation

	inst0_reg_8bits: reg_8bits	PORT MAP -- component instantiation
		(aclr, n_write, data, sel_word(0), word0);
		
	inst1_reg_8bits: reg_8bits	PORT MAP -- component instantiation
		(aclr, n_write, data, sel_word(1), word1);
		
	inst2_reg_8bits: reg_8bits	PORT MAP -- component instantiation
		(aclr, n_write, data, sel_word(2), word2);
		
	inst3_reg_8bits: reg_8bits	PORT MAP -- component instantiation
		(aclr, n_write, data, sel_word(3), word3);
	
	inst4_reg_8bits: reg_8bits	PORT MAP -- component instantiation
		(aclr, n_write, data, sel_word(4), word4);
		
	inst5_reg_8bits: reg_8bits	PORT MAP -- component instantiation
		(aclr, n_write, data, sel_word(5), word5);
		
	inst6_reg_8bits: reg_8bits	PORT MAP -- component instantiation
		(aclr,n_write, data, sel_word(6), word6);
		
	inst7_reg_8bits: reg_8bits	PORT MAP -- component instantiation
		(aclr,n_write, data, sel_word(7), word7);


END SYN;