###########################################################################
#
# Generated by : Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
#
# Project      : Skiroc2
# Revision     : Skiroc2
#
# Date         : Thu Apr 26 15:28:27 CEST 2018
#
###########################################################################
 
 
# WARNING: Expected ENABLE_CLOCK_LATENCY to be set to 'ON', but it is set to 'OFF'
#          In SDC, create_generated_clock auto-generates clock latency
#
# ------------------------------------------
#
# Create generated clocks based on PLLs
derive_pll_clocks -use_tan_name
#
# ------------------------------------------


# Original Clock Setting Name: clk_osc
create_clock -period "25.000 ns" \
             -name {clk_osc} {clk_osc}
# ---------------------------------------------

# ** Clock Latency
#    -------------

# ** Clock Uncertainty
#    -----------------

# ** Multicycles
#    -----------
# ** Cuts
#    ----

# ** Input/Output Delays
#    -------------------




# ** Tpd requirements
#    ----------------

# ** Setup/Hold Relationships
#    ------------------------

# ** Tsu/Th requirements
#    -------------------


# ** Tco/MinTco requirements
#    -----------------------

#
# Entity Specific Timing Assignments found in
# the Timing Analyzer Settings report panel
#
set_false_path -from [get_keepers {*dcfifo_9ei1*|write_delay_cycle[*]}] -to [get_keepers {*dcfifo_9ei1*|*dffpipe_rs_dgwp|*dffpipe9|dffe10a[*]}]
set_false_path -from [get_keepers {*dcfifo_elh1*|write_delay_cycle[*]}] -to [get_keepers {*dcfifo_elh1*|*dffpipe_rs_dgwp|*dffpipe3|dffe4a[*]}]
set_false_path -from [get_keepers {*dcfifo_gai1*|write_delay_cycle[*]}] -to [get_keepers {*dcfifo_gai1*|*dffpipe_rs_dgwp|*dffpipe9|dffe10a[*]}]
set_false_path -from [get_keepers {*dcfifo_pdi1*|write_delay_cycle[*]}] -to [get_keepers {*dcfifo_pdi1*|*dffpipe_rs_dgwp|*dffpipe9|dffe10a[*]}]


# ---------------------------------------------

