The slow control is a shift register composed of n flip flops (n = 829 flip flops in MAROC3). Data are stored in flip flops on leading edge of the clock. The data are shifted at each clock cycle as seen on Figure 3.

Slow control register parameters

SC nameSC descriptionSub adressRecommendations
ON/OFF_otabg power pulsing bit for bandgap 0 not active on MAROC3 test board  because power pulsing pin is connected to vdd
ON/OFF_dac power pulsing bit for all DACs 1 not active on MAROC3 test board  because power pulsing pin is connected to vdd
small_dac to decrease the slope of DAC0 -> better accuracy 2 small dac OFF: threshold VTH0  min= and max=                                                 small dac ON: threshold VTH0 min=   and max=
DAC2[9] DAC value for the second discri (with the fast shaper FSB2) 3  
DAC2[8] 4  
... ...  
DAC2[1] 11  
DAC2[0] 12  
DAC1[9] DAC value for the first discri (with the fast shaper FSB1 or FSU) 13  
DAC1[8] 14  
... ...  
DAC1[1] 21  
DAC1[0] 22  
enb_outADC wilkinson ADC parameter: enable data output 23 to use the wilkinson ADC should be OFF
inv_startCmptGray wilkinson ADC parameter:  the start compteur polarity switching 24 to use the wilkinson ADC should be OFF
ramp_8bit wilkinson ADC parameter: ramp slope change to have quickly conversion on 8 bits 25  
ramp_10bit wilkinson ADC parameter: ramp slope change to have quickly conversion on 10 bits 26  
mask _OR2_ch63 mask the second discri output of ch63  (FSB2 to generate the trigger) 27 mask bit ON: no trigger output , mask bit OFF: trigger output visible
mask_OR1_ch63 mask the first discri output of ch63 (FSB1 or FSU to generate the trigger) 28 mask bit ON: no trigger output , mask bit OFF: trigger output visible
mask _OR2_ch62 mask the second discri output of ch62  (FSB2 to generate the trigger) 29  
mask_OR1_ch62 mask the first discri output of ch62 (FSB1 or FSU to generate the trigger) 30  
...   ...  
mask _OR2_ch1 mask the second discri output of ch1  (FSB2 to generate the trigger) 151  
mask_OR1_ch1 mask the first discri output of ch1 (FSB1 or FSU to generate the trigger) 152  
mask _OR2_ch0 mask the second discri output of ch0  (FSB2 to generate the trigger) 153  
mask_OR1_ch0 mask the first discri output of ch0 (FSB1 or FSU to generate the trigger) 154  
cmd_CK_mux   155 Should be OFF
d1_d2 trigger output choice 156 d1_d2='0' -> trigger from FSB1 and DAC1 ;  d1_d2='1' -> trigger from FSB2 and DAC2
inv_discriADC ADC discri output could be inverted 157 Should be OFF
polar_discri polarity of trigger output 158 polar_discri='0' ->High polarity ; polar_discri='1' -> Low polarity
Enb_tristate enable all trigger outputs 159 Should be ON to see trigger outputs
valid_dc_fsb2 enable FSB2 DC measurements 160  
sw_fsb2_50f Feedback capacitor for FSB2 161 better if ON
sw_fsb2_100f Feedback resistor for FSB2 162  
sw_fsb2_100k Feedback resistor for FSB2 163  
sw_fsb2_50k Feedback resistor for FSB2 164  
valid_dc_fs enable FSB and FSU DC measurements 165  
cmd_fsb_fsu Choice between FSB1 or FSU for the first discri input (with DAC0) 166 cmd_fsb_fsu='1'-> FSU ; cmd_fsb_fsu='0'-> FSB
sw_fsb1_50f Feedback capacitor for FSB1 167 better if ON
sw_fsb1_100f Feedback capacitor for FSB1 168 better if ON
sw_fsb1_100k Feedback resistor for FSB1 169  
sw_fsb1_50k Feedback resistor for FSB1 170  
sw_fsu_100k Feedback resistor for FSU 171  
sw_fsu_50k Feedback resistor for FSU 172  
sw_fsu_25k Feedback resistor for FSU 173  
sw_fsu_40f Feedback capacitor for FSU 174 better if ON
sw_fsu_20f Feedback capacitor for FSU 175 better if ON
H1H2_choice ADC wilkinson: choice between the first or the second track and hold for the input of the ADC 176  
EN_ADC ADC wilkinson: enable ADC conversion inside the asic 177 Should be ON to make a conversion
sw_ss_1200f Feedback capacitor for Slow Shaper 178  
sw_ss_600f Feedback capacitor for Slow Shaper 179  
sw_ss_300f Feedback capacitor for Slow Shaper 180  
ON/OFF_ss Power supply of Slow Shaper 181  
swb_buf_2p capacitor for the buffer before the slow shaper 182  
swb_buf_1p capacitor for the buffer before the slow shaper 183  
swb_buf_500f capacitor for the buffer before the slow shaper 184  
swb_buf_250f capacitor for the buffer before the slow shaper 185  
cmd_fsb enable signal at the FSB inputs 186 Should be ON if we want to use FSB1 or FSB2
cmd_ss enable signal at the SS inputs 187 Should be ON if we want to do charge measurement
cmd_fsu enable signal at the FSU inputs 188 Should be ON if we want to use FSU
cmd_SUM63 enable signal to do sum 189  
GAIN63[7] preamplifier gain value channel 63 190  
GAIN63[6] 191  
GAIN63[5] 192  
GAIN63[4] 193  
GAIN63[3] 194  
GAIN63[2] 195  
GAIN63[1] 196  
GAIN63[0] 197  
cmd_SUM62 enable signal to do sum 198  
GAIN62[7] preamplifier gain value channel 63 199  
GAIN62[6] 200  
GAIN62[5] 201  
GAIN62[4] 202  
GAIN62[3] 203  
GAIN62[2] 204  
GAIN62[1] 205  
GAIN62[0] 206  
...   ...  
GAIN0[5] preamplifier gain value channel 0 759  
GAIN0[4] 760  
GAIN0[3] 761  
GAIN0[2] 762  
GAIN0[1] 763  
GAIN0[0] 764  
Ctest_ch63 enable signal in Ctest input 765  
Ctest_ch62 enable signal in Ctest input 766  
Ctest_ch61 enable signal in Ctest input 767  
... enable signal in Ctest input ....  
Ctest_ch2 enable signal in Ctest input 826  
Ctest_ch1 enable signal in Ctest input 827  
Ctest_ch0 enable signal in Ctest input 828  

Distributed worldwide by

CAEN

Maroc 3A download

You are not logged in.
Most technical files and detailed product description are accessible only to logged users.

Maroc 3A - contact

Need advice ?

Contact us

JB cizel identite

Maroc 3product manager is
Jean-Baptiste Cizel

 

Login to My Weeroc

You are not logged in to My Weeroc and might not be able to see all information

please login to have full access

Login to My Weeroc

Please login to access to all information, download center and MyWeeroc